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352 I/O IC FPGA

CHUANGXINDA ELECTRONICS-TECH CO., LIMITED
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352 I/O IC FPGA

Brand Name : Xilinx Inc.

Model Number : XC4VFX40-10FFG672I

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 6000~7500 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 92 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : Programmable Logic ICs

Condition : Original 100%,Brand New and Original,New

Number of I/Os : 352 I/O

Product : Virtex-4

Package / Case : FBGA-672

Distributed RAM : 291 kbit

Embedded Block RAM - EBR : 2592 kbit

Maximum Operating Frequency : 500 MHz

Service : BOM Kitting

Lead time : In Stock,contact us

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XC4VFX100-11FFG1517I IC FPGA FBGA-1517 768 I/O 500 MHz Virtex-4

Product Attribute Attribute Value
Xilinx
FPGA - Field Programmable Gate Array
Virtex-4
41904
352 I/O
1.2 V
- 40 C
+ 100 C
SMD/SMT
FBGA-672
Data Rate: 6.5 Gb/s
Series: XC4VFX40
Brand: Xilinx
Distributed RAM: 291 kbit
Embedded Block RAM - EBR: 2592 kbit
Maximum Operating Frequency: 500 MHz
Moisture Sensitive: Yes
Number of Transceivers: 12 Transceiver
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 1
Subcategory: Programmable Logic ICs
Tradename: Virtex

Summary of Virtex-4 FPGA Features

The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface),
tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry,
and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible.
Virtex-4 devices are produced on astate-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology
• Up to 960 user I/Os
• Wide selections of I/O standards from 1.5V to 3.3V

• Extremely high-performance
- 600 Mb/s HSTL & SSTL (on all single-ended I/O)
- 1 Gb/s LVDS (on all differential I/O pairs)

• True differential termination
• Selected low-capacitance I/Os for improved signal integrity
• Same edge capture at input and output I/Os
• Memory interface support for DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• Cascadable embedded XtremeDSP slices with 18-bit x 18-bit dedicated multipliers, integrated Adder, and
48-bit accumulator.

352 I/O IC FPGA


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